Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture
نویسندگان
چکیده
| Decreasing capacitance of bus lines is one of the e ective ways to reduce whole power dissipation of LSIs. In this paper we compare microprocessors designed based on a bus architecture and a multiplexer architecture in terms of power dissipation and delay time. Through implementation of a test chip, the multiplexer architecture is e ective to reduce power dissipation by about 30%.
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